VHDL 作业问题，请教各位大神了

conv_std_logic_vector(aint,8);

u_or: OR2 PORT MAP(a=>d, b=>e, c=>f);

LIBRARY IEEE；

USE IEEE.Std_logic_1164.ALL；

ENTITY display IS

   PORT(di：IN Std_logic_vector(3 DOWNTO 0)；

                a，b，c，d，e，f，g：OUT Std_logic)；

END display；

ARCHITECTURE behavl_49 OF display IS

    SIGNALx:Std_logic_vector(6 DOWNTO 0)；

BEGIN

     PROCESS(di)

     BEGIN

            CASEdi IS

                    WHEN ″0000″ => x <= B″011_1111″；         -- 0

                    WHEN″0001″ => x <= B″000_0110″；         -- 1

                    WHEN″0010″ => x<= B″101_1011″；         -- 2

                    WHEN″0011″ => x <= B″100_1111″；         --3

                    WHEN″0100″ => x <= B″110_0110″；         -- 4

                    WHEN″0101″ => x <= B″110_1101″；         --5

                    WHEN″0110″ => x <= B″111_1101″；         --6

                    WHEN″0111″ => x <= B″010_0111″；         --7

                    WHEN″1000″ => x <= B″111_1111″；         --8

                    WHEN″1001″ => x<= B″110_1111″；         --9

                    WHENOTHERS=> x <= (OTHERS => ′0′)； -- 熄灭

               END CASE；

         END PROCESS；

        a<= NOT x(0)；

        b <= NOT x(1)；

        c <= NOT x(2)；

        d <= NOT x(3)；

        e <= NOT x(4)；

        f <= NOT x(5)；

        g <= NOT x(6)；

END behavl_49；

如果上面的描述中有些字符是全角字符的话，将其改为半角字符之后，就可以通过编译了。